1. Field of the Invention
The present invention relates to driving apparatus and methods, plasma display apparatus, and power supply circuits for plasma display panel, suitable for, e.g., AC-driven plasma displays.
2. Description of the Related Art
In recent years, demand has increased for replacing CRTs with flat matrix type display apparatus such as PDPs (Plasma Display Panels), LCDs (Liquid Crystal Displays), and ELDs (Electro-Luminescence Displays) in terms of decreased thickness. In particular, AC-driven PDPs are excellent in visibility because they are self-emission type displays. They can make display on a large screen with a thin device. Thus they have received a great deal of attention as a next-generation display that can realize higher image quality than CRTs.
Conventionally well-known AC-driven PDPs are classified into two-electrode type PDPs performing selective discharge (address discharge) and sustain discharge with two electrodes, and three-electrode type PDPS performing address discharge further using a third electrode. The three-electrode type PDPs are further classified into PDPs having its third electrode formed on the same substrate as its first and second electrodes, and PDPs having its third electrode formed on another substrate opposite to the substrate of its first and second electrodes.
All types of PDP apparatus described above are based on the same principle. Thus the construction of a PDP apparatus will be described below wherein first and second electrodes for performing sustain discharge are formed on a first substrate, and a third electrode is separately prepared on a second substrate opposite to the first substrate.
FIG. 1 is a diagrammatic view showing the whole construction of an AC-driven PDP apparatus. Referring to FIG. 1, an AC-driven PDP 1 is provided with parallel scanning electrodes Y1 to Yn and common electrodes X formed on one surface, and address electrodes A1 to Am formed on the opposite surface so as to be perpendicular to the electrodes Y1 to Yn and X. Each common electrode X is disposed close to its corresponding one of the scanning electrodes Y1 to Yn. The common electrodes X are commonly connected to one terminal.
The common terminal of the common electrodes X is connected to the output terminal of an X-side circuit 2. The scanning electrodes Y1 to Yn are connected to the output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to the output terminals of an address-side circuit 4. The X-side circuit 2 comprises a circuit for repeating a discharge. The Y-side circuit 3 comprises a circuit for line-sequential scan, and a circuit for repeating a discharge. The address-side circuit 4 comprises a circuit for selecting a line to be displayed. These X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled with control signals from a control circuit 5. More specifically, the address-side circuit 4 and the circuit for line-sequential scan in the Y-side circuit determine cells to be lit, and the display of the PDP is made by repeating discharges of the X- and Y-side circuits 2 and 3.
The control circuit 5 generates the control signals on the basis of external display data D, a clock CLK representing read timing for the display data D, a horizontal sync signal HS, and a vertical sync signal VS, and supplies the control signals to the X-side circuit 2, the Y-side circuit 3, and the address-side circuit 4.
FIG. 2A is a sectional view of a cell Cij as one pixel, which is in the i-th row and the j-th column. Referring to FIG. 2A, a common electrode X and a scanning electrode Yi are formed on a front glass substrate 11. The structure is coated with a dielectric layer 12 for insulating the electrodes from a discharge space 17. The resultant structure is further coated with an MgO (magnesium oxide) protective film 13.
An address electrode Aj is formed on a back glass substrate 14 opposite to the front glass substrate 11. A dielectric layer 15 is formed on the address electrode Aj. The dielectric layer 15 is coated with a fluorescent substance. The discharge space 17 between the MgO protective film 13 and the dielectric layer 15 is charged with Ne+Xe Penning gas.
FIG. 2B is for explaining a capacitance Cp in the AC-driven PDP. Referring to FIG. 2B, in the AC-driven PDP, capacitance components Ca, Cb, Cc appear in the discharge space 17, between the common and scanning electrodes X and Y, and within the front glass substrate 11, respectively. The sum of them gives the capacitance Cpcell per cell (Cpcell=Ca+Cb+Cc). The total of the capacitances Cpcell of all cells gives the panel capacitance Cp.
FIG. 2C is for explaining fluorescence in the AC-driven PDP. Referring to FIG. 2C, fluorescent substances for red, blue, and yellow are applied to be arranged each color in stripes on the inside surfaces of a ribs 16. A discharge between common and scanning electrodes X and Y excites the corresponding fluorescent substance 18 to fluoresce.
FIG. 3 is a timing chart showing voltage waveforms in a driving method of the AC-driven PDP. FIG. 3 shows one of subfields making up one frame. One subfield is divided into a reset period consisting of a full write period and a full erase period, an address period, and a sustain discharge period.
First in the reset period, all the scanning electrodes Y1 to Yn are set at the ground level (0 V). Simultaneously with this, a full write pulse having a voltage Vs+Vw (about 400 V) is applied to the common electrodes X. At this time, all the address electrodes A1 to Am are at a potential Vaw (about 100 V). As a result, discharge occurs in every cell of every display line to generate wall charges, independently of the preceding display state.
Next, the potentials of the common electrodes X and the address electrodes A1 to Am become 0 V. The voltage by wall charges themselves then exceeds the discharge start voltage in every cell, and discharge starts. This discharge makes no wall charge because there is no difference in potential between electrodes. Space charges are neutralized by themselves to end discharge. This is so-called self-erase discharge. By this self-erase discharge, all cells in the panel become a uniform state free from wall charges. This reset period serves to set all cells in the same state independently of the ON/OFF state of each cell in the preceding subfield. This makes it possible to perform the subsequent address (write) discharge stably.
Next, in the address period, address discharge is line-sequentially performed to turn each cell ON/OFF in accordance with display data. More specifically, a voltage at xe2x88x92Vy level (about xe2x88x92150 V) is applied to the scanning electrode Y1 corresponding to the first display line, and a voltage at xe2x88x92Vsc level (about xe2x88x9250 V) is applied to the scanning electrodes Y2 to Yn corresponding to the remaining display lines. At the same time, an address pulse having a voltage Va (about 50 V) is selectively applied to an address electrode Aj corresponding to a cell to undergo sustain discharge, i.e., to be turned ON, in the address electrodes A1 to Am.
Consequently, discharge occurs between the scanning electrode Y1 and the address electrode Aj of the cell to be turned ON. With this priming (pilot), discharge between the scanning electrode Y1 and the corresponding common electrode X having a voltage Vx starts immediately. An amount of wall charges enough for the next sustain discharge is then stored on the surface of the MgO protective film 13 on the common electrode X and the scanning electrode Y1 of the selected cell. Similarly for the scanning electrodes Y2 to Yn corresponding to the remaining display lines, the voltage at xe2x88x92Vy level is applied to the scanning electrodes of selected cells in order, and the voltage at xe2x88x92Vsc level is applied to the remaining scanning electrodes of non-selected cells. New display data is thereby written in all display lines.
In the subsequent sustain discharge period, a sustain pulse having the voltage Vs (about 200 V) is alternately applied to the scanning electrodes Y1 to Yn and the common electrodes X to perform sustain discharge. An image of one subfield is displayed. The luminance of the image is determined by the length of the sustain discharge period, i.e., the number of times or the frequency of sustain pulse application.
In such an AC-driven PDP, the voltage Vf at which a gas discharge starts between the surfaces of the common and scanning electrodes X and Y, is within the range of 220 to 260 V in general. Within an address period, e.g., in a cell to display, the voltage is applied between the address and scanning electrodes A and Y to make a gas discharge occur. Using it as a trigger, a discharge is made to occur between the common and scanning electrodes X and Y, so as to leave wall charges on the common and scanning electrodes X and Y in the cell.
In the subsequent sustain discharge period, with the wall charges Vwall generated in the address period, and the sustain pulse voltage Vs applied between the common and scanning electrodes X and Y, a gas discharge can be made to occur by setting |Vs+Vwall| at Vf or more. The value of the voltage Vs is not more than the discharge start voltage Vf. A voltage value that |Vs| less than |Vf| less than |Vs+Vwall| is used as Vs.
When a gas discharge once occurs between the common and scanning electrodes X and Y, the wall charges on the common and scanning electrodes X and Y in the cell are replaced by wall charges in the reverse polarity to end the gas discharge. Thus a sustain pulse voltage Vs in the polarity reverse to the previous one is applied between the common and scanning electrodes X and Y. A gas discharge thereby occur again using the wall charges newly generated on the common and scanning electrodes X and Y. By repeating the above operations, the gas discharges can be repeated.
The above-described xe2x80x9cwrite address methodxe2x80x9d is an example of driving method for such an AC-driven PDP, in which the wall charges of all cells in the panel are erased in a reset period, and cells to display are selectively subjected to discharges in the subsequent address period to accumulate wall charges. Contrastingly in xe2x80x9cerasion address methodxe2x80x9d as another example, wall charges are accumulated in relation to all cells in the panel in a reset period, and cells not to display are selectively subjected to discharges in the subsequent address period to erase their wall charges, thereby leaving wall charges only in cells to display.
FIG. 4 is a circuit diagram showing a partial construction of a driving apparatus for the conventional PDP apparatus. Referring to FIG. 4, a load 20 represents the total capacitance of the cells formed between one common electrode X and one scanning electrode Y. The load 20 is provided with a common electrode X and a scanning electrode Y, to which pulse voltages described with FIG. 3 are applied by the X-side circuit 2 and the Y-side circuit 3.
The X-side circuit 2 includes a power supply circuit 21, a power recovery circuit 22, and a sustainer circuit 23. The power supply circuit 21 comprises a diode D1 connected to the power supply line of the sustain pulse voltage Vs, transistors Tr1 and Tr2 connected in series between the ground (GND) and the power supply line of the write voltage Vw, and a capacitor C1, connected between the common drain of the transistors Tr1 and Tr2 and the output of the diode D1.
To apply the full write pulse to the common electrodes X in the reset period, the transistor Tr1 is turned ON, and the transistor Tr2 is turned OFF. The sustain pulse voltage Vs having passed through the diode D1 and the write voltage Vw are summed and supplied to the sustainer circuit 23. To apply the sustain pulse to the common electrodes X in the sustain discharge period, the transistor Tr1 is turned OFF, and the transistor Tr2 is turned ON. The sustain pulse voltage Vs having passed through the diode D1 is directly supplied to the sustainer circuit 23.
The sustainer circuit 23 comprises a switch circuit made by a parallel connection of a transistor Tr5 and a diode D5, two diodes D7 and D8 connected in series to the switch circuit, and a switch circuit made by a parallel connection of a transistor Tr6 and a diode D6 and connected in series to the diode D8. The node between the diodes D7 and D8 is connected to the common electrode X of the load 20.
When the transistor Tr5 is ON and the transistor Tr6 is OFF, the sustain pulse voltage Vs or the full write pulse voltage Vs+Vw supplied from the power supply circuit 21 is applied to the common electrode X. Contrastingly, when the transistor Tr5 is OFF and the transistor Tr6 is ON, the ground level voltage (0 V) is applied to the common electrode X.
The power recovery circuit 22 comprises two coils L1 and L2 connected to the capacitive load 20 of the PDP through the respective diodes D7 and D8, a diode D3 and a transistor Tr3 connected in series to one coil L1, a diode D4 and a transistor Tr4 connected in series to the other coil L2, and a capacitor C2 connected between the ground and the common terminal of the transistors Tr3 and Tr4.
The capacitive load 20 and the two coils L1 and L2 connected to the load 20 through the two diodes D7 and D8 form two series of resonance circuits. More specifically, the power recovery circuit 22 has two series of L-C resonance circuits. The power recovery circuit 22 is for recover the charges supplied by a resonance of the coil L1 and the capacitive load 20, by a resonance of the coil L2 and the capacitive load 20.
The Y-side circuit 3 includes a scan driver 31, a sustainer circuit and power supply circuit 32, and a power recovery circuit 33. The scan driver 31 comprises two transistors Tr7 and Tr8 connected in series. The node between the two transistors Tr7 and Tr8 is connected to the scanning electrode Y of the load 20. A scan pulse voltage xe2x88x92Vy, a non-selection pulse voltage xe2x88x92Vsc, or a sustain pulse voltage Vs supplied from the power supply circuit 32 described later is applied to the scanning electrode Y.
The sustainer circuit and power supply circuit 32 comprises transistors Tr9 and Tr10 connected to the power supply line of the scan pulse voltage xe2x88x92Vy, a transistor Tr11 and a diode D9 connected to the power supply line of the non-selection pulse voltage xe2x88x92Vsc, a transistor Tr12 connected to the power supply line of the sustain pulse voltage Vs, a transistor Tr13 connected to the ground for leakage control, and a transistor Tr14 and diode D14 for disconnecting the power supply line of the scan pulse voltage xe2x88x92Vy and non-selection pulse xe2x88x92Vsc, from a GND line.
By appropriately controlling ON/OFF of each of the transistors Tr7 to Tr14 of this sustainer circuit and power supply circuit 32 and scan driver 31, the scan pulse voltage xe2x88x92Vy, the non-selection pulse voltage xe2x88x92Vsc, or the sustain pulse voltage Vs is applied to the scanning electrode Y, as shown in FIG. 3.
The power recovery circuit 33 comprises two coils L3 and L4 connected to the capacitive load 20 through the respective transistors Tr7 and Tr8, a diode D12 and a transistor Tr15 connected in series to one coil L3, a diode D13 and a transistor Tr16 connected in series to the other coil L4, and a capacitor C3 connected between the ground and the common terminal of the transistors Tr15 and Tr16.
This power recovery circuit 33 also has two series of L-C resonance circuits. The power recovery circuit 22 is for recover the charges supplied by a resonance of the coil L1 and the capacitive load 20, by a resonance of the coil L2 and the capacitive load 20.
FIG. 5 is a circuit diagram showing an example of the conventional constructions of a line-sequentially scanning circuit in the Y-side circuit 3, and discharge repeating circuits in the X- and Y-side circuits 2 and 3.
Referring to FIG. 5, each of switches SW1 and SW2 comprises FETs connected in parallel. The switch SW1 is connected to a power supply Vs. A power recovery circuit including coils L1 and L2, switches SW3, SW5, and SW6, and a capacitor C1 is provided on the common electrode X side. A switch SW7 is connected between a power supply Vax and the common electrode X.
On the scanning electrode Y side, a scan driver including switches SW20 and SW21 is connected to the scanning electrode Y. On the switch SW20 side of the scan driver, a power supply Vsc is connected through a switch SW18, and a switch SW11 is connected. On the switch SW21 side of the scan driver, a power supply (xe2x88x92Vy) is connected through switches SW16 and SW17, and the ground terminal is connected through a switch SW19. On the switch SW21 side, a diode D1 and switches SW10 and SW15 are connected between the switch SW21 and the power supply Vs, as shown in the drawing.
An A/S separation circuit for isolating the circuit for line-sequential scan (for address) and the circuit for repeating a discharge (for sustainer) is made up from a diode D2 provided on the switch SW20 side of the scan driver, and a switch SW15 provided on the switch SW21 side of the scan driver. Also on the scanning electrode Y side, a power recovery circuit is provided which comprises coils L3 and L4, switches SW12, SW13, and SW14, and a capacitor C2.
FIG. 6 shows an example of construction of a high-voltage power supply necessary for the above circuit shown in FIG. 5. Referring to FIG. 6, as the values of the voltages Vs, Vax, Vy, and Vsc, respectively used are 180 V, 50 V, xe2x88x92180 V, and xe2x88x9280 V, which are high voltages.
FIG. 7 is a timing chart showing an operation of the above circuit shown in FIG. 5. In a scanning period, the switches SW16, SW17, and SW18 on the scanning electrode Y side are turned ON to apply a voltage Vsc (=100 V) between both terminals of the scan driver. Further, the switch SW21 is turned ON to apply a voltage (xe2x88x92Vy=xe2x88x92180 V) to one scanning electrode Y which is the scanning target, and the switch SW20 is turned ON to apply a voltage (Vscxe2x88x92Vy=xe2x88x9280 V) to the remaining scanning electrodes Y.
At the intersection between the scan pulse of 180 V to the one scanning electrode Y which is the scanning target, and each address electrode A, e.g., in case of making a display, a gas discharge is made to occur by a voltage Va (=60 V) applied to the address electrode A. Using the gas discharge between the address and scanning electrodes A and Y as a trigger, a discharge is further made to occur between the common electrode X (to which a voltage Vax is applied by turning the switch SW7 ON) and the scanning electrode Y (to which a voltage of xe2x88x92180 V is applied). Wall charges different in polarity from the applied voltages are thereby generated on the dielectric layer 12 on the scanning electrodes X and Y shown in FIG. 2. This operation is performed to every scanning electrode Y.
The A/S separation circuit is for preventing a short circuit between the diode D1 and the switch SW16 in its ON state due to the voltage (xe2x88x92Vy) that is lower than the ground level, and for preventing a short circuit between the switch SW18 and a diode parasitic on the switch SW11 due to the voltage Vsc that is lower than the ground level. During the above operation, the switch SW15 is kept OFF. A voltage of 180 V is applied between both terminals of the switch SW15.
In the subsequent sustain discharge period, the switches SW12 and SW15 on the scanning electrode Y side are turned ON, and the switch SW2 on the common electrode X side is turned ON. An L-C resonance thereby occurs by the coil L3 and the capacitance Cp of the PDP panel with using the capacitor C2, whose one terminal is always grounded, as a power supply. The voltage on the scanning electrode Y side is raised near Vs. Next, the switch SW10 is turned ON to raise the voltage to Vs, and thereby the voltage being applied to the scanning electrode Y is set at Vs. At this time, the voltage Vs (=180 V) is applied between both terminals of the switch SW11, which is being OFF.
The voltage Vs being applied between the common and scanning electrodes X and Y is thereby added to a voltage due to wall charges generated in the above-described scanning period, and so a gas discharge starts. The current then flows through the switches SW10, SW15, and SW2. At this time, wall charges are again generated as described above.
Next, on the scanning electrode Y side, the switches SW10 and SW12 are turned OFF, and the switch SW13 is turned ON. An L-C resonance thereby occurs by the coil L4 and the capacitance Cp of the PDP panel with using the capacitor C2, whose one terminal is always grounded, as a power supply. The voltage on the scanning electrode Y side is lowered near the ground level. Next, the switch SW11 is turned ON to lower the voltage to the ground level, and thereby the voltage being applied to the scanning electrode Y is set at the ground level. At this time, the voltage Vs (=180 V) is applied between both terminals of the switch SW 10, which is being OFF.
Next, the switch SW3 on the common electrode X side is turned ON. An L-C resonance thereby occurs by the coil L1 and the capacitance Cp of the PDP panel with using the capacitor C1, whose one terminal is always grounded, as a power supply. The voltage on the common electrode X side is raised near Vs. Next, the switch SW1 is turned ON to raise the voltage to Vs, and thereby the voltage being applied to the common electrode X is set at Vs. At this time, the voltage Vs (=180 V) is applied between both terminals of the switch SW 2, which is being OFF.
The voltage Vs being applied between the common and scanning electrodes X and Y is thereby added to a voltage due to wall charges generated some time ago, and so a gas discharge starts. The current then flows through the switches SW1 and SW11. At this time, wall charges are again generated as described above.
Next, on the common electrode X side, the switches SW1 and SW3 are turned OFF, and the switch SW6 is turned ON. An L-C resonance thereby occurs by the coil L2 and the capacitance Cp of the PDP panel with using the capacitor C1, whose one terminal is always grounded, as a power supply. The voltage on the common electrode X side is lowered near the ground level. Next, the switch SW2 is turned ON to lower the voltage to the ground level, and thereby the voltage being applied to the common electrode X is set at the ground level. At this time, the voltage Vs (=180 V) is applied between both terminals of each of the switch SW 1 on the common electrode X side and the switch SW10 on the scanning electrode Y side, which are being OFF.
The breakdown voltages of various elements of the driving apparatus are determined by the maximum voltage of the pulse to be applied to the elements. In the conventional driving apparatus, a fixed voltage supplied from the power supply lines is applied to the load. For example, one of the X and Y electrodes is set at the ground level and the fixed voltage is applied to the other. For this reason, each element in the driving apparatus must have a high breakdown voltage corresponding to the fixed voltage.
In particular, in case of the construction shown in FIG. 4, each element making up the sustainer circuit 23 in the X-side circuit 2, requires a very high breakdown voltage corresponding to the full write pulse voltage Vs+Vw (about 400 V). Thus an expensive and large switching element such as a FET must be used to ensure a sufficient breakdown voltage. This causes a complex circuit construction and a very high manufacturing cost.
Besides, in case of the construction shown in FIG. 5, the breakdown voltage of each FET of the switches SW1, SW2, SW10, SW11, and SW15, must be Vs or more. In addition, each FET of those switches is for controlling a gas discharge current, so it must have a low ON voltage for a stable gas discharge. However, generally in FETs, the higher the breakdown voltage is, the higher the ON voltage is (in case of double the breakdown voltage, proportionally to the third to fourth power of two). For this reason, in order to drive the PDP stably, it is required to dispose FETs in parallel in each of the switches SW1, SW2, SW10, SW11, and SW15 for controlling a gas discharge current, so as to decrease its ON voltage. Thus a higher breakdown voltage causes an increase in cost of each FET. Besides, an increase in the number of FETs causes a further increase in cost. Further, for realizing such waveforms as shown in FIG. 7 by the circuit of FIG. 5, four kinds of high-voltage power supplies are required. This also causes an increase in cost.
Besides, a fixed voltage to be applied to the load is very high. For this reason, when charging or discharging is performed in relation to the capacitance of the load, a very large power loss occurs.
It is an object of the present invention to provide driving apparatus and methods wherein the breakdown voltage of each element of the driving apparatus is held down (i.e., minimized), thereby realizing simplification in circuit construction and reduction of manufacturing cost.
It is another object of the present invention to reduce the power consumption when charging or discharging is performed in relation to the capacitance of the load.
A driving apparatus according to the present invention comprises a first signal line for applying a voltage at a first level to a load, and a second signal line for applying a voltage at a second level to the load, wherein the voltage of the second signal line is set at a third level and the voltage of the first signal line is set at the first level to apply the voltage at the first level to the load through the first signal line, and the voltage of the first signal line is set at the third level and the voltage of the second signal line is set at the second level to apply the voltage at the second level to the load through the second signal line.
The present invention having the above technical feature makes it possible for a power supply, which generates a voltage less than a predetermined to be applied to the load, to generate the voltages at the first and second levels, the absolute values of which are less than that of the predetermined voltage. Selectively applying those voltages to the load substantially achieves application of the predetermined voltage to the load. The voltage applied to each element in the driving apparatus is then the first or second level voltage at most, so the breakdown voltage of each element can be hold down in comparison with its conventional value. This makes it possible to use inexpensive small elements and so realize simplification in circuit construction and reduction of manufacturing cost.
Besides, the voltage to be applied to the load is sufficed by the voltages at the first and second levels, whose absolute values are less than that of the predetermined voltage. Thus the power consumption can be reduced in comparison with the conventional manner, in which the predetermined voltage itself is applied to the load.